Reset Search
 

 

Article

BIST FAILURE: POW_BIST_STAT, error bits ((bist_val & mask) ^ expected): 0x20000 on boot

« Go Back

Information

 
TitleBIST FAILURE: POW_BIST_STAT, error bits ((bist_val & mask) ^ expected): 0x20000 on boot
Question
What does BIST FAILURE: POW_BIST_STAT, error bits ((bist_val & mask) ^ expected): 0x20000 mean?
Environment
Summit Switch
Answer
Submit RMA 

To learn more about the RMA process go to: Return Material Authorization RMA Process and FAQ
Additional notes
Full error message output:

Copyright 2014 Extreme Networks, Inc.
 
BIST FAILURE: POW_BIST_STAT, error bits ((bist_val & mask) ^ expected): 0x20000
BIST Errors found (1).
'1' bits above indicate unexpected BIST status.
 
Press and hold the <spacebar> to enter the bootrom:  0
Loading Secondary OS Image
 
Copyright 2014 Extreme Networks, Inc.
 
Starting CRC of Default image
Using Default image ...
 
Copyright 2014 Extreme Networks, Inc.
 
BIST FAILURE: POW_BIST_STAT, error bits ((bist_val & mask) ^ expected): 0x20000
BIST Errors found (1).
'1' bits above indicate unexpected BIST status.
 
Press and hold the <spacebar> to enter the bootrom:  0
Loading Secondary OS Image
 

Feedback

 

Was this article helpful?


   

Feedback

Please tell us how we can make this article more useful.

Characters Remaining: 255