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Summit X670V-48t generating “Failed programming EEPROM with eee set enable error” message in switch logs

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TitleSummit X670V-48t generating “Failed programming EEPROM with eee set enable error” message in switch logs
Symptoms
  • Summit X670V-48t generating “Failed programming EEPROM with eee set enable error” message in switch logs. 

-> show log
01/25/2018 14:25:41.23 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=47, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.23 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=48, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.16 <Erro:HAL.Port.Error> Failed to set eee config on port 48, rv = -16
01/25/2018 14:25:41.16 <Erro:HAL.Port.Error> Failed to set eee config on port 47, rv = -16
01/25/2018 14:25:41.15 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=4, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.15 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=3, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.15 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=2, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.15 <Erro:Kern.Error> bcm_custom_extr_eee_config_set(18175): eee set enable error, port=1, unit=0, enable=0, rv=-16
01/25/2018 14:25:41.15 <Crit:Kern.Alert> 0:4 Failed programming EEPROM.
01/25/2018 14:25:41.15 <Crit:Kern.Alert> 0:3 Failed programming EEPROM
.
01/25/2018 14:25:41.15 <Crit:Kern.Alert>
01/25/2018 14:25:41.15 <Crit:Kern.Alert> Warning: Loss of power during this process may render the ports unusable.
01/25/2018 14:25:41.15 <Crit:Kern.Alert>
01/25/2018 14:25:41.15 <Crit:Kern.Alert> PHY firmware update required.  This process may take up to 15 minutes.
01/25/2018 14:25:41.15 <Crit:Kern.Alert> 0:4 Unable to load firmware from EEPROM.
01/25/2018 14:25:41.15 <Crit:Kern.Alert> 0:3 Unable to load firmware from EEPROM.

Environment
  • Summit X670V-48t
  • EXOS 16.2.4.5patch1-3
  • EXOS 16.2.4.5patch1-5
Cause
Resolution
  • Try to run the diagnostics test on failed switch and verify if it is a hardware failure referring the below output:

Loading Diagnostics ... |/
Running Image ...Decompressing diagnostics...
Initializing operational diagnostics...
Initializing operational diagnostics...
FAN module 1 detected.
FAN module 2 detected.
FAN module 3 detected.
SOC unit 0 attached to PCI device BCM56846_A1
BCM8481X/8482X: u=0 p=3: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=4: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=5: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=6: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=7: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=8: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=9: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=10: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=11: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=12: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=13: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=14: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=15: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=16: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=17: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=18: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=19: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=20: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=21: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=22: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=23: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=24: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=25: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=26: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=27: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=28: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=29: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=30: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=31: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=32: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=33: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=34: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=35: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=36: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=37: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=38: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=39: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=40: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=41: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=42: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=43: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=44: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=45: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=46: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=45 id0=0x362 id1=0x5fd0
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=46 id0=0x362 id1=0x5fd0
Initializing operational diagnostics...
FAN module 1 detected.
FAN module 2 detected.
FAN module 3 detected.
SOC unit 0 attached to PCI device BCM56846_A1
BCM8481X/8482X: u=0 p=3: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=4: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=5: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=6: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=7: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=8: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=9: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=10: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=11: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=12: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=13: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=14: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=15: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=16: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=17: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=18: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=19: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=20: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=21: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=22: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=23: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=24: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=25: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=26: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=27: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=28: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=29: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=30: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=31: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=32: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=33: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=34: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=35: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=36: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=37: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=38: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=39: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=40: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=41: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=42: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=43: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=44: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=45: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=46: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=45 id0=0x362 id1=0x5fd0
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=46 id0=0x362 id1=0x5fd0
Initializing operational diagnostics...
FAN module 1 detected.
FAN module 2 detected.
FAN module 3 detected.
SOC unit 0 attached to PCI device BCM56846_A1
BCM8481X/8482X: u=0 p=3: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=4: init. Chip Rev = 00 Version = 01.66 Date = 02/08/2013 (MDIO)
BCM8481X/8482X: u=0 p=5: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=6: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=7: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=8: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=9: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=10: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=11: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=12: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=13: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=14: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=15: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=16: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=17: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=18: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=19: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=20: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=21: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=22: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=23: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=24: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=25: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=26: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=27: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=28: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=29: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=30: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=31: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=32: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=33: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=34: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=35: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=36: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=37: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=38: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=39: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=40: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=41: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=42: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=43: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=44: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=45: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
BCM8481X/8482X: u=0 p=46: init. Chip Rev = 01 Version = 01.57 Date = 07/25/2012 (SPI)
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=45 id0=0x362 id1=0x5fd0
_phy_8481_xaui_nxt_dev_probe: found phy device u=0 p=46 id0=0x362 id1=0x5fd0
Initializing operational diagnostics...
FAN module 1 detected.
FAN module 2 detected.
FAN module 3 detected.
SOC unit 0 attached to PCI device BCM56846_A1

  • If the above mentioned error messages generated. It is an hardware failure and we can proceed with switch replacement.
  • PHY is hardware layer on OSI layer. For more information check this URL: https://en.wikipedia.org/wiki/PHY_(chip)
  • For more information contact GTAC for assistance.
Additional notes

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